Dc motor speed control with motor voltage and current sensing means

ABSTRACT

This disclosure is directed to a feedback control for a D.C. shunt motor for motoring and regenerating modes of operation. The motor armature is connected to a three-phase A.C. input by a pair of full wave bridge networks connected in parallel and having silicon controlled rectifiers in each leg. Input and feedback signals are summated to an error signal which is then summated with a cemf signal to establish a control signal connected to actuate a gating regulating means which in turn controls firing of the controlled rectifiers of the two bridges with a zero current firing angle control. The gating regulator connected to the rectifier is a &#39;&#39;&#39;&#39;nor&#39;&#39;&#39;&#39; logic current for each unit and includes a zero current detector in combination with an intercept detector which provides an output during the proper half cycle of the applied voltage and further transmits a signal in accordance with the desired phase angle for firing of the controlled rectifier.

United States Patent 1 11 3,716,771 Maynard 1 Feb. 13, 1973 [5 DC MOTORSPEED CONTROL WITH Primary Examiner-Bernard A. Gilheany MOTOR VOLTAGEAND CURRENT SENSING MEANS Related Application Data [22] Filed:

Inventor:

Assignee:

Appl. No.2

Continuation of Ser. No. 713,247, March 14, 1968,

abandonedsignal which is then summated with a cemf signal to establish acontrol signal connected to actuate a gating [52] US. Cl ..318/33lregulating means which in mm controls firing of the [51] II). C]. ..H02p5/16 controlled rectifiers of the two b i g with a Zero p [58] Fleld ofSearch ..318/331, 332, 345, 338 mm firing angle comm [56] Refere Cit dThe gating regulator connected to the rectifier is a nor" logic currentfor each unit and includes a zero UNlTED STATES PATENTS current detectorin combination with an intercept de- 3,181,050 4/1965 Berman ..3l8/33ltectof which P i an output during the P P 3,599,064 8/:971 Friedman t i318/331 cycle of the applied voltage and further transmits a 3,234,68311/1966 Black .-3l8/332 signal in accordance with the desired phaseangle 'for %??2 g gihkefson firing of the controlled rectifier. 3, l l 6l a an l 3 7 16 Claims, 5 Drawing Figures 2/ Y 22 COMMAND ERROR fSUMMING SIGNAL r AMPILIFIER AMPLIFIER |/24 7 v, ISOLATING a gJ 1 1 LFILTERING CIRCUIT i SENSING NEGATIVE 4/ NETWORK ]1 E 32a POLAR REFERENCI N;UT l: /4 DETECTOR TRANSFORMER TRANSFORMER I I M g 1 /e Posmve Q l I[I 7 BRDGE 222242; a L a 7 29 r r I 58 INTERCEPT l I GATE GATE 27DETECTOR L DRIVER, DRIVER I (40 5a L I NOR 57 MONOSTABLE 26 I DETECTOR 2a l ggi ggg INVERTER NOR MONOSTABLE I i 47 j 46 9 INVERTER r44 L.

l DUPLICATE GATE l CIRCUITS Assistant Examiner-Thomas LangerAttorney-Andrus, Sceales, Starke 8L Sawall ABSTRACT Input and feedbacksignals are summated to an error PATENTEU FEM 31973 SHEET 2 BF 4INVENTOR.

J 7- Maynard PATENTEDFEB13|975 5,716,771

SHEET k UF 4 F65. 5. T0 DETECTOR 58 TO DETECTOR 59 INVENTOR J hn 77Maynard BY DC MOTOR SPEED CONTROL WITH MOTOR VOLTAGE AND CURRENT SENSINGMEANS This application is a continuation application of application Ser.No. 713,247 filed on Mar. 14, 1968 and entitled DYNAMOELECTRIC CONTROLCIR- CUIT, now abandoned.

' This invention relates to a dynamoelectric control circuit andparticularly to a control circuit for regulating the armature voltage ofa direct current motor while supplying the required demand current formotoring or regenerating loads.

Direct current motors and the like are employed in controland drivesystems and generally include some form of a feedback system to controlthe input power to the motor and thereby the motor speed or output. Adirect current shunt motor is highly desirable where a relativelyconstant speed is desired with a high starting torque; for example,where fairly heavy loads are encountered. The shunt motor mayconveniently have fixed field excitation and an armature current controlproviding the desired speed and torque control.

The torque or speed of a shunt motor can be controlled by changing thevoltage applied to the field, the voltage applied to the armature orboth. The voltage supplied to the armature may be convenientlycontrolled withthe recently developed solid state devices such assilicon controlled rectifiers of either the unilateral or bilateralconduction variety both of which allow effective varying of theconnection of a polyphase voltage supply to the armature.

One of the severe problems encountered in motor controls however is theprovision of a truly linear control and one which permits operation ofthe motor automatically in either a motoring mode or a regeneratingmode. Thus, a direct current motor when being driven by a load functionsas a generator and it is highly desirable to permit regeneratingoperation of the motor whereby the electrical power generated is fedback into the supply lines.

With the development of the silicon controlled rectitier and other gatedelectronic solid state switches, a great plurality of motor controlcircuits have been suggested to selectively control the power supplyconnection of an electrical load including the armature winding of shuntmotors and the like. However, applicant knows of no control circuitwhich provides a highly linear control and which can be applied to awide range of motor sizes.

The present invention is particularly directed to a highly linearcontrol for a direct current load and particularly a direct currentshunt motor for maintaining the motor output torque and speed withinexceptionally close tolerances and generally of the order of one-half,one or two per cent, if necessary.

Generally, in accordance with the present invention, an analog controlsystem is provided, providing an analog input signal and an analogfeedback signal. The input and feedback signals are summated to providea summated error signal which is then summated with a signal inaccordance with the counter-electromotive force (cemf or counter emf) ofthe direct current dynamoelectric load to control the application ofpower to the armature. The summated control signal is interconnected toactuate a gating regulating means which in turn is interconnected tocontrol phased-firing of a solid state gated network interconnecting themotor to an alternating current source. By proper firing of the gatednetwork, the necessary power is supplied to the motor to maintainpredetermined operating conditions.

The summated counter-electromotive force signal and error signalestablishes a novel zero current firing angle control to effectivelyconnect the power supply to the armature at the proper time. Thus, thecemf signal establishes an effective zero crossover or gating point forzero armature current and continuously adjusts the reference level fromwhich the error signal causes the application of voltage to the armatureand thus provides variation in the input in accordance with both thecemf and the actual error signals.

The gating regulating means is arranged such that in the absence of anycounter-electromotive force, the firing is established at the zerocrossover point of the applied voltage. The zero crossover point is thatpoint in time when the applied anode voltage goes from positive tonegative for the particular silicon controlled rectified. in order toobtain load current, the firing of the rectifiers is advanced from thezero current crossing point to fire during the positive half cycle. Thetrue or effective zero current crossing point varies with line voltageand counter emf and the device is advanced with respect to sucheffective point only when there is an error signal and further inaccordance with the magnitude of such error signal.

in order to provide reversible motor operation, as well as regenerativeoperation, a gated network includes a pair of full wave bridge networksconnected in parallel to the armature and employing triggered switchmeans such as silicon controlled rectifiers or any other similarlyfunctioning means interconnected to the motor to selectively conductarmature currents in either direction and thereby establishcorresponding opposite torques. The dual gated networks permit operatingof the motor in either direction with either a motoring or aregenerative mode of operation. The circuit automatically senses themode on the basis of an error signal and selects the proper network toestablish the related armature current. Each of the bridge networks isgenerally interconnected in a similar manner to the gated regulatormeans. A polarity sensitive circuit senses the summated error signalderived from the command signal and the feedback signal to determinewhich of the two networks operate.

Generally, in accordance with the present invention, the gatingregulating means is a digital signal generator having a logic circuitfor each of the gated devices of the bridge networks. The logic circuitincludes-a zero current detector in combination with an interceptdetector interconnected into a Nor type logic unit which provides anoutput during the proper half cycle of the applied voltage and furthertransmits a signal in accordance with the desired phase angle. The zerocurrent and intercept detectors provide logic signals which limit theeffective firing of the rectifiers to an operative period whichcorresponds to the period the anode of the rectifier is positive. Theintercept detector is connected to the summated control signal andprovides a logic signal todetermine precisely within such operativeperiod when the rectifiers are fired. The output of the logic circuitfires a pulse forming circuit such as a monostableor rapid triggercircuit which in turn is preferably connected through a gate drivingcircuit to the proper gated rectifier or devices.

Further, applicant has found that in order to obtain a highly accuratelinear control, an A.C. reference voltage related to that applied to therectifiers and connected to the intercept detector should be shifted tolead the voltage applied to the rectifiers by thirty degrees. In orderto provide proper synchronized firing, the intercept detector includesan internal direct current bias circuit to compensate for the phasedisplacement and effectively return the firing to the original zerocrossover point of the main applied voltage. This has been found toprovide a highly linear response characteristic; i.e. the characteristicbetween the command signal and the power supplied to the motor isessentially a straight line in the continuous current conduction mode.This is very important in order to maintain stability and properoperation in the high current region of the motor circuit or'the likeand further to permit full output in the presence of thecounter-electromotive force.

Further, in accordance with the circuit, applicant has found that thecounter emf component which is fed back into the control system shouldbe modified for optimum functioning such that the armature current isessentially directly proportional to the error signal and independent ofthe absolute value or amplitude of the counter emf. Applicant has foundthat this modification can be controlled by providing a proper selectionand modification of the primary and secondary voltages of the inputtransformer and proper proportion of I R feedback.

The present invention provides a highly reliable solid state controlparticularly adapted to control a shunt motor within close tolerancesand having a linear and sensitive response.

The drawings furnished herewith illustrate a preferred construction ofthe present invention in which the above advantages and features areclearly disclosed as well as others which will be clear from thefollowing description.

In the drawings:

FIG. 1 is a block diagram of a motor control circuit constructed inaccordance with the present invention;

FIG. 2 is a graphical illustration showing the gating characteristicsfor a gated bridge network;

FIG. 3 is a graphical illustration of the voltage signals at certainpoints in the circuit shown in FIG. 1;

FIG. 4 is a schematic circuit diagram of selected components shown inFIG. 1 in block diagram; and

FIG. 5 isa schematic circuit illustrating a preferred rectifier bridgeand input power supply circuit.

Referring to the drawings and particularly to FIG. I, the presentinvention is illustrated applied to control the speed of a directcurrent shunt motor 1 of any well known construction. The illustratedshunt motor is diagrammatically shown including a field 2 connected to afixed excitation source 3. An armature 4 is rotatably mounted within thefield 2 and is connected to a direct current power supply circuit 5which includes a pair of gated rectifier bridge networks 6 and 7 toselectively provide forward and reverse current to the armature 4. Theinput sides of the bridge networks 6 and 7 are connected in parallel tothree phase power source lines 8 which may, for example, be the widelyemployed industrial 440 volt alternating current. As more fullydeveloped hereinafter, the bridge networks 6 and 7 include gated devicessuch as silicon controlled rectifiers or the like to vary the appliedvoltage and the magnitude of the corresponding armature current. Bridgenetwork 6 establishes a given directional flow with the resulting torqueproviding a motoring action in one direction, or, if the motor isoverdriven and functioning as a generator, a braking or regeneratingaction. Bridge network 7 establishes the opposite directional currentwith a corresponding motoring or regenerating action. A digital gatingregulator 9, forming a part of a control or regulating circuit 10, isinterconnected to the bridge networks 6 and 7 to selectively control thefiring and conductivity thereof. A command signal unit 11 provides adirect current input voltage proportional to the desired energization ofthe motor 1. The output of unit 11 is interconnected in a unique mannerto a voltage feedback signal line 12 and a current feedback signal line13 to control the gating regulator 9 and thereby the armature current.

More particularly in FIG. 1, three phase bridge input lines 14 areparallel connected to the bridge networks 6 and 7 which, as shown inFIG. 5, may be the standard three phase full wave gated bridge circuitsemploying silicon controlled rectifiers or other gated devices. Thethree phase input lines 14 are connected to the power supply lines 8through an input transfonner 15 preferably of a wye to wye variety.

A commutation and oscillation filter network 16 is interconnected to theoutput side of the transformer 15 to protect the bridge circuits duringcommutation from one branch to another and to protect against voltagetransients which may be introduced into the system as a result ofswitching circuits and the like.

Inductors 17 are connected one in each of the phase lines between thenetwork 16 and the input lines 14. A current sensing network 18 is alsoconnected to the lines from network 16 and may include isolating andfilter means such that the current feedback line 13 connected to networkl8 provides a signal proportional to the total armature current.

Line voltage is thus simultaneously applied across both of the bridgenetworks 6 and '7, only one of which is conditioned to conduct as aresult of obtaining a proper signal from the digital gating regulator 9depending upon the desired rotation or torque of the motor 1, assubsequently described.

The control circuit 10 includes an error amplifier 19 which in theillustrated embodiment may be any suitable negative gain operationalamplifying circuit having a pair of inputs one of which is connected tothe command signal unit 11 and the other of which is connected to thevoltage feedback line 12. The error umplifier 19 is selected to have asubstantial gain or beta; a beta of the order of 68 has been foundsatisfactory in one practical circuit. The output of the error amplifier19 is proportional to the difference in the command signal and thevoltage feedback signal multiplied by the gain of the error amplifier19.

A voltage isolating and filtering circuit 20 is connected to the circuitof the armature 4 of the motor 1 to provide an isolated DC. signalproportional to the armature voltage. This signal is passed throughcircuit 20 to eliminate the ripple component inherent in the output ofthe armature and to provide an essentially pure D.C. signal at thefeedback line 12. The feedback signal is also scaled by the circuit inaccordance with the command signal range. Thus, for example, the voltageapplied to the D.C. motor may be of the order of 500 volts D.C. whereasthe command signal may be in the order of plus or minus 10 volts D.C.Consequently, the armature voltage must be scaled down to give acorresponding related signal.

The amplified output signal of the error amplifier is connected via anoutput line 21 to the input of a multiple input summing amplifier 22.

The summing amplifier is a suitable operational amplifier adapted toalgebraically summate a plurality of D.C. signals and may have a beta ofl. A second input of the summing amplifier 22 is connected to thecurrent feedback line 13 and a third input is connected by a line 23 tothe voltage feedback line 12.

As the resistance of the armature is fixed, or constant, the currentfeedback signal at line 13 provides a signal proportional to thearmature losses which is, of course, equal to the armature current timesthe armature resistance. Consequently, the difference between thevoltage proportional signal at line 12 and the current proportionalsignal at line 13 is proportional to the counter-electromotive force ofthe armature. The output of the summing amplifier 22 appearing at line24 is therefore equal to. the summated error signal andcounter-electromotive force signal and may be conveniently written Vg iBAV The control signal line 24 is interconnected to the digital gatingregulator9 to apply this summated signal to the regulator and control.

the firing of the bridge networks 6 and 7.

The digital gating regulator 9 is specially constructed in accordancewith the present invention to provide a zero current firing or trackingsystem and generally includes six similargate boards or circuits 25 eachof which is similarly constructed to provide a pair of output signals.As each of the gate boards 25 is similarly constructed, only one isshown with detailed block diagram in FIG. 1. The output of circuit 25includes a forward bridge gate line 26 interconnected to a gate driver27 for controlling selected gated rectifier elements of the bridgenetwork 6 and a second or reverse bridge gate line 28 is similarlyinterconnected to a gate driver 29 for the network 7.

Before describing the detail of the gate board 25, the theory of thetriggering control is further described in connection with the graphicalillustration in FIG. 2 wherein the Y-axis is a voltage scale and theX-axis is a time scale.

An alternating current sine wave voltage curve 30 is illustrative of theanode voltage applied to the silicon controlled rectifiers or similargates devices in each of the networks 6 and 7.

A trigger reference AC. voltage curve or trace 31 which is applied tothe gating regulator 9 is shown on a corresponding time scale. Thereference voltage is employed to control firing of networks 6 and 7 andthereby the flow of current in the armature 4. The trigger referenceA.C. curve 31 is displaced 30 (after filtering) withrespect to thevoltage curve 30 applied to the bridge network to provide improvedlinearity of control. A direct current fixed bias forming a part ofregulator 9 in the illustrated embodiment and particularly board 25 issuperimposed on the reference voltage as shown by line 32.

it is noted that the fixed D.C. bias is selected to establish interceptof the reference voltage curve 31 with the fixed bias level line 32 insynchronism with the zero crossover point 33 of the bridge voltage curve30. In the absence of a counter emf and/or an error signal, this is theproper point at which to fire the related gated portion of networks 6and 7 for zero current. To obtain load current, the gate firing must beadvanced ahead of the zero current firing point. Further, the true zerocurrent point, which is when the anode voltage changes from positive tonegative relative to the cathode voltage varies with the counter emf andline voltage. To provide proper and continuous tracking of the effect, adirect current signal of an appropriate polarity is provided as shown bya positive counter-electromotive force line 34 and a correspondingnegative counterelectromotive force line 35. The signal 34 or 35 adds tothe D.C. fixed bias voltage and the intersection with the curve 31establishes the true zero current firing point.

Referring toFIG. 2, the thirty degree offset of the filtered referencesignal curve 31 establishes its maximum peak in phase with the sixtydegree angle of the positive half cycle of the anode voltage curve 30.In a full wave three phase system, the 60 point of any one phase voltageis the first point at which conduction can start because of the otherphase voltages. The error signal which may also be positive or. negativeprovides a further direct current bias in the circuit at any given timeor instance. In FIG. 2, only a positive error signal is shownsuperimposed upon the positive counter emf to define motor interceptline 36 and upon the negative counter emf line to define regenerateintercept line 37. The gate signal is to be established whenever thecurve 31 intercepts the D.C. level line 36 or 37.

For any given counter-electromotive force and error signal, the motoringintercept point 38 occurs during the positive half cycle and is phasedback from the zero current intercept established by the counter emfsignal line 34 in accordance with the magnitude of the error. Forregenerative action, the regenerate intercept point 39 occurs during therelatively negative half cycle of the bridge voltage and properly biasesthe bridge network 6 and 7 to conduct the regenerative current andreturn the power to the supply lines. When the motor intercept line 36or the regenerated intercept line 37 is at or above the peak of thereference curve 31, the gating regulator 9 establishes a tire or gatepulse at the peak of the reference signal and produces maximum output.

The digital gating regulator 9 provides the desired interaction in theillustrated embodiment of the invention as shown in block diagram inFIG. 1 where the six similar gate boards 25 are provided and one ofwhich is shown with the several components identified by labeled blocks.The details of a preferred construction being shown in FIG. 4 andsubsequently described. The board or circuit 25 is a digital logiccircuit. The logic circuit may employ a binary notation system and isdescribed with a negative voltage logic having a 0" voltage signal asOY' level and a negative I voltage signal as the l level in accordancewith the circuit of FIG. 4. Further, the illustrated control circuit ofFIG. 4 employs PNP type transistor elements and requires a referencesignal input which is phase-shifted 180 with respect to signal curve 31.To maintain simplicity of subsequent description, FIG. 1 is furtherdescribed with the above logic and the several output curves properlyshown in FIG. 3, with the curves operatively corresponding to those ofFIG. 2 similarly numbered.

The circuit 25 includes a zero detector circuit or module 40 which isconnected to an anode voltage reference transformer 41. The zerodetector reference voltage curve 42 is phase shifted by 60 lag withrespect to the anode voltage curve 30 to limit the proper gate pulsefiring range for maximum gate signal advance when motoring, and themaximum retard when regenerating. The output of the zero detector module40 is a square wave signal 43 which in binary notation is at l levelwhen the A.C. anode reference voltage curve 42 is positive and at alevel for the opposite 180 thereof. The output of the zero detectormodule 40 is applied to a logic inverter module 44, the output of whichis an inverted square wave signal as shown at 45 in FIG. 3. The outputof the inverter module is applied as one input of a two input Nor logiccircuit module 46. In accordance with well known logic circuitconnections, the Nor" circuit 46 is such that the output will be at 0signal in the presence of a l signal at either input and provide a 1"level or signal output only when there is a 0 signal applied to-bothinputs.

The second input of the Nor circuit 46 is interconnected to the summatedcontrol signal from the summing amplifier 22 through an interceptdetector module 47. i

The intercept detector module 47 is a further logic circuit having oneinput interconnected to the reference signal from the anode voltagereference transformer 41 and a second input connected to the signal line24 to receive the summated signals of the counter emf signal and theerror signal. The detector module 47 internally-includes a D.C. biascontrol to provide the D.C. fixed bias shown by line 32 in FIGS. 2 and3. The internal D.C. bias effectively vertically displaces the referencevoltage curve 42 zero crossing such that the zero axis intercept isshifted 30 as shown by the new axis or direct current reference dashedline 32. The output of the intercept detector module 47 is a square wavesignal 48 similar to that of the zero detector module but displacedtherefrom by 120 when error signal and counter emf are zero andtherefore from the anode reference voltage curve by the 180 previouslynoted. Further, because of the D.C. bias, the square wave is notsymmetrical but is at a zero level for the period the reference wave isnegative with respect to the zero reference line 32. The output of thedetector module is fed to a logic inverter circuit or module 49 whichprovides a curve as shown at 50 in FIG. 3. The output of the invertermodule 49 is applied as the second input to the two input Nor" module46, the output of which is interconnected to control a monostablecircuit or logic module '51. The output of signal, the output of theNor" circuit becomes 1". The zero detector module 40 thus establishes atiming mark" which effectively includes the last of the anode referencecurve positive half cycle and restricts firing control to the first 60of the negative half cycle, producing a maximum control range of (120for motoring mode, and 60 for regenerative mode of operation).

An input into the monostable circuit 51 generates a timed pulse such asshown by curve 53 which in turn is applied to the gate driver 27 togenerate a triggering pulse as shown by curve 54 in any suitablewell-known manner. The output of the driver 27 is connected to tirenetwork 6. In FIG. 3, pulse 53 occurs at the time the anode referencecurve 31 passes through zero. This assumes there is nocounter-electromotive force signal and/or error signal.

If the motor is operating at a speed corresponding to the commandsignal, a counter-electromotive force signal would be superimposed uponthe D.C. bias and establish the line 34. This would advance the firingpulse and cause it to fire at the point in the applied anode voltagewhich equals the counter-electromotive force and produce the proper zerocurrent angle. If, however, there is an error signal which is summatedwith the counter-electromotive force and establishes the D.C. line 36 toadvance the firing angle from the zero current angle point and thussupply the necessary demand current.

If the errorshould cause the line 34 to exceed the peak value of thereference voltage of curve 31, a pulse 53 is established in synchronismwith the peak which in turn corresponds to the 60 angle of the anodevoltage curve 30. In a three phase system, this corresponds to maximumoutput capability and the regulator thus is continuous to providemaximum current until the error decreases to again produce an interceptwith curve 31.

Simultaneously with the above generation of a transfer signal or of apulse signal for gating a network 6, a corresponding signal is providedfor network 7 from an intercept detector module 55 which has its outputconnected directly to a Nor circuit or logic module 56. The Nor logicmodule 56 has its second input connected directly to the output of thezero detector module 40 which forms a common control element for both ofthe bridge networks 6 and 7. The output of the Nor" logic module 56'issimilarly connected to a monostable circuit 57 which produces acorresponding train of pulse signalsfor the bridge network 7. Thesepulses will be phase shifted 180 with respect to the pulses 52 and 53 asa result of the elimination of the inverter modules 44 and 49 from thecircuit channel relating to detector 55 Following the same reasoning asjust given for network 6, it will be understood that network 7 respondsto a negative error signal to amplifier 19 to conduct and establish anopposite torque.

Which of the two bridge networks 6 and 7 operates is determined by apair of polarity detecting units 58 and 59 which are connected inparallel to the output of the error operational amplifier 19 and inparticular to line 21. The positive error signal detector unit 58 hasits output interconnected to the monostable circuits 51 for the bridgenetwork 6 and the detector unit 59 is similarly connected to themonostable modules 57 for the bridge network 7. The detector units 58and 59 are suitable polarity sensitive logic devices which will enablethe proper circuit in response to the polarity of the error signal.Thus, a positive error signal will be sensed by the detector 58 toenable the bridge network 6 and simultaneously the negative detectorunit 59 will disable the bridge network 7. Conversely if the errorsignal of amplifier 19 is negative, the network 6 will be disabled andnetwork 7 enabled.

The operation of the circuit shown in FIG. 1 is briefly summarized asfollows. As previously noted, network 6 always provides armature currentin one direction and network 7 always in the opposite direction. Thepolarity of the error signal directly determines which network is tofunction for either motoring or regenerating acas long as the commandsignal exceeds the armature voltage. Conversely, if the command signalis negative to establishing motoring in the opposite direction, theerror signal is negative and bridge network 7 is properly fired as longas the command signal exceeds the armature voltage.

The dual networks 6 and 7 provide for reversible rotation of the motorwith either the motoring mode or alternatively a regenerating mode ofoperation. The bridge network 6 is assumed to produce a currentestablishing a clockwise torque and bridge network 7 is assumed toproduce a counterclockwise torque. in the operation of the illustratedcircuit, if the motor is rotating in a clockwise direction, bridgenetwork 6 is fired for the motoring mode of operation and the bridgenetwork 7 for the regenerating mode. Conversely, if the motor isrotating counterclockwise, bridge network 7 is fired for the motoringmode of operation and bridge network 6 for the regenerating mode.Further, the polarity of the amplified error signal which isproportional to the command signal and the voltage error signal directlydetermines and properly fires one of the two networks 6 and 7 and duringthe proper half cycle of the alternating current input. For example, ifthe command signal is positive to command network 6 but the motor forsome reason is overdriven in the motoring direction, the counter emfsignal which is negative becomes greater than the command signal andreverses the polarity of the error signal. This changes the firing fromthe network 6 to network 7. Further, the signal is added to thecorresponding'DC. bias and places the intercept on the positive halfcycle of the network 7 for regenerative action. if the load shouldactually reverse the direction of rotation, the counter emf signalreverses and is added to the DC. bias line and causes the intercept tomove up the positive half cycle of the reference voltage curve 31 fornetwork 6 and triggers the network to conduct during the negative halfcycle of the applied voltage curve and thereby supply energy to thepower source with a resulting regenerating or braking action.

The system thus automatically selects and energizes the proper bridgenetwork 6 or 7 for motoring or regenerating mode of operation inresponse to the incoming command signal and the closed loop armaturevoltage feedback signal into the error amplifier 19. The

firing in the absence of an error signal and a counterelectromotiveforce signal is at the zero crossover point of the anode referencevoltage waveform as shown in FIG. 3. If a positive counter-electromotiveforce is present, the counter-electromotive force signal issuper-imposed upon the reference and defines the new zero interceptpoint or line 34 and establishes a corresponding zero current firingpoint. When fired at this point, the output of the SCR network will bezero. In order to obtain a' load current from the bridge network 6, thegate firing must be advanced in time ahead of the zero current firingpoint. The degree of advance for load current is controlled by the errorsignal which is superimposed upon the DC. bias level and the counter emflevel to establish the control intercept line 36. If the error signal issufficiently great there is no intercept output and the logic to the Normodule 46 is held at a 0" level. As a result of the zero detector module40, the digital gating regulator generates a pulse at each maximum ofthe reference voltage 31 and applied a trigger pulse to the gatingnetwork to fire the network at a angle of the applied anode voltage wavecorresponding to the maximum possible voltage of the applied voltagebecause the several phases of a three phase system intercept at the 60point for any given phase voltage. The maximum voltage applied to thearmature provides maximum current and torque; for example, duringstarting when the error signal is a maximum. As the motor begins tooperate, the counterelectromotive force increases and the related signalfed through the control circuit. Also, the armature voltage signal whichis fed back via the feedback line 12 to the error operational amplifier19 is reduced. The counterelectromotive force is applied to the summingoperational amplifier and the output of the summing operationalamplifier will then be equal to the summation of the error signal andthe counter-electromotive force.

Generally, until the armature counter-electromotive force equals thedesired operating level, maximum allowable firing of the SCRs ismaintained. Thereafter, the firing is established to essentiallymaintain the zero crossover point with respect to the desiredcounterelectromotive force. The regulating digital gating regulator 9may automatically control the armature voltage to within plus or minus 2percent while delivering any current within the rating of the motorregardless of line voltage or ambient temperatures.

The forward network 6 and may be assumed to establish clockwise torquewhile the network 7 is associated with the provision of acounterclockwise torque. Thus, if the input command signal is positive,

clockwise torque is maintained to provide motoring torque. If, however,the load should overrun the desired operating point determined by thecommand signal and result in an overrunning torque on armature 4, themotor functions as a generator and the unit automatically providesregenerative braking torque. The negative signal added to the DC biasshifts the firing point to the negative half cycle of the network. Thenetwork 6 is thereby fired to conduct in a direction to permit transferof the energy from the motor 1 to the supply line 8. The motor 1 is thenoperating in a regenerating or braking mode.

The illustrated embodiment of the invention provides a direct voltagesystem to particularly control the armature voltage under all operatingconditions. If desired, with proper modification and provision ofexternal current components, a similar speed control can be provided.The present invention, in a most novel aspect, resides in the use of theoperational amplifier to provide an error signal in combination with the.summing amplifier to modify the error signal in accordance with thearmature counter-electromotive force and thereby providing an analogsignal which properly controls a digital gating regulator to fire eitherof a pair of gated networks to control all possible anodes of operatinga dynamoelectric machine.

The digital gating regulator and associated circuitry is more fullydisclosed in a practical construction in FIG. 4 for driving a full wavebridge power circuit shown in FIG. 5.

Referring particularly to FIG. 5, the bridge networks 6 and 7 are shownemploying well-known silicon controlled rectifier devices with sixsilicon controlled rectifiers 60 through 65in bridge network 7 and 66through 71 inclusive in bridge network 6. The silicon controlledrectifiers 6071 are properly connected in pairs between the output lines72 and 73 connected to the armature 4 with the junction of each pair ofrectifiers interconnected to a related phase line 14. Each of thenetworks 6 and 7 provides a full wave three phase rectified output ofthe output lines with the bridge networks 6 and 7 connected in parallel.Each of the control rectifiers is similarly constructed with the anode74 and cathode 75 properly connected between a phase line 14 and anoutput line 72 or 73. The gate 76 of each silicon controlled rectifierfor conductingphase to phase voltages are interconnected to the gatedrivers 27 and 29 for proper firing of silicon controlled rectifierpairs for sequential conduction of the three phase input. As the gatedriver may take any desired configuration or design, a particularcircuit is not shown in the illustrated embodiment of the invention. Apreferred pulsing circuit is shown in applicants copending application,Ser. No. 682,185, now U.S. Pat. No. 3,535,610, entitled GATING SYSTEMFOR CONTROLLED RECTIFIER MEANS, which is assigned to a common assigneeand which was filed on Nov. [3, 1967.

In any structure, the output of the regulator 9 will provide pulsesignals to fire the appropriate silicon con: trolled rectifiers inresponse to the summated error and feedback signals.

The intercept detector module 47 is a multiple stage high gaindifferential amplifier and particularly includes four cascadedtransistors 77, 78, 79 and 80. The illustrated transistors 7780 are ofthe PNP variety and are connected to suitable positive and negative DC.power supply lines 81 and 82 as well as a ground or reference line 83through suitable biasing resistors and the like. The differentialconfiguration holds the base 84 of transistor 77 near ground intheabsence of a selected summated input signal. The input transistor 77 hasits base 83 connected to the negative supply line 81 through a resistivenetwork 85 including an adjustable resistor 86. The resistive network 85establishes the proper D.C.bias which in accordance with an actualembodiment of the invention equaled one half the peak value of. thealternating current input. Clamping diodes 87 and 88 are connectedback-to-back parallel relation between the base 84 and a ground orreference line 83 to prevent excessive saturation of the amplifier. Apair of resistors 89 and 90 are connected in series with each other tothe base 84 and to an alternating current reference signal line 91. Acapacitor 92 is connected between the junction of the resistors andground line 83 and with resistors establishes a lag filter to shift thesignal at line 91 and establish a signal corresponding to curve 31 inFIG. 3. A lag filter is required because of the convenient constructionof transformer 41 which provided a signal input at resistor 89 leadingthe anode reference voltage by 60 and which therefore had to bedecreased by thirty degrees to establish the desired voltage wave 31 totransistor 77 A resistor 93 is connected to the output of the summingamplifier 22 via the line 24 and constitutes a third input to thetransistor 77.

The various input resistors are selected to convert the signal voltagesinto related individual currents such that the current at the base isthe sum of the individual currents flowing through the three resistivepaths. As the gain of the transistors 77-80 is substantial, a very smallsummated current at the base results in driving of the output transistor80 into saturation thereby driving its collector or output terminal toground, corresponding to the 0 level shown at 48 in FIG. 3.

The amplifying stages of the module 47 provide a high impedance, lowhysteresis detector responsive to the summing current input. Thus, ifthe sum of the currents is sufficient to bias the transistor 77 on, thetransistor 80 provides an output essentially ground potential. Thiscorresponds to a logic zero level. If the transistor 77 is cut off, theoutput rises to a logic 1 level or a negative 10 volts in a practicalcircuit.

The output of the intercept detection module is connected to theinverter 49 which in FIG. 4 is shown as a common emitter connectedtransistor 94 of a PNP variety suitably interconnected to the D.C.supply and having its base connected to the output of the transistor 80.When the transistor 80 conducts to hold its output at essentiallyground, the converter transistor 94 is cut off and conversely when thetransistor is cut off the transistor 94 conducts. This reverses thelogic at the output of the transistor 94 with respect to the summatedsignal inputs to transistor 77.

A resistor 95 interconnects the output of the transistor 94 to atransistor 96 which constitutes the two input Nor circuit or module 46in FIG. I. The second input to transistor 96 is from the zero detectormodule 40.

The zero detector module 40 shown in FIG. 4 includes an input transistor97 having an input circuit connected to the .altemating currentreference source through a resistive-capacitive filter network 98. Thistends to reduce the sensitivity to noise and transients while addingonly a minimal degree of phase lag into the circuit. A limiting diode 99is also connected to the input circuit.

Atransistor 100 constitutes the inverter logic device 44 of FIG. 1 andis connected to the output of the transistor 97. The transistor 100 isconnected to the bias supply through a suitable temperature stabilizingresistive network including a resistor 101 connected between the baseand positive bias potential to hold the transistor off under hightemperature conditions and with a zero logic input.

In operation, when the A.C. reference input goes negative by abouta'minus 1 volt, an appreciable base current flows to turn on thetransistor 97 and establishing the collector at reference or groundlevel thereby producing a output. Conversely, when the input voltage isslightly above the minus 1, the transistor is cut off and the output isat a relatively negative level corresponding to logic I level. The logicinverter transistor 100 which inverts the logic and provides a logic 0signal only during the negative half cycle and a logic 1 signal duringthe positive cycle of the reference voltage. The logic signals areapplied as the second input to the Nor transistor 96. If either or bothinputs are at a logic one level corresponding to a negative voltage,then the output of the transistor 96 is at ground and a logic 0.However, when and only when both inputs are at a logic 0 level, theoutput of the Nor transistor 96 becomes negative corresponding to thelogic 1 signal. The Nor transistor 96 is normally at a logic 0 and canrise to a logic l level only during the positive half cycle of thereference input. The precise point at which itso raises being controlledby the signal from the intercept response transistor 80.

. The output of the Nor transistor 96 is interconnected to control arelated monostable logic circuit which in the illustrated embodiment isshown consisting of a pair of transistors 102 and 103 interconnected ina known circuit with transistor 102 cut off and transistor 103conducting. In operation, when the output of the Nor transistor 96changes from the ground or 0 logic to a negative or logic I level, thetransistor 102 is biased on and grounds a capacitor 104 which turns offthe normally'conducting transistor 103 resulting in a negative level atthe output of the transistor 103 and establishes a logic 1" output fromthe monostable circuit for a selected period. The bias network of themonostable circuit includes suitablebias resistors to insure thattransistor 102 is held off in the absence of a proper input signal fromtransistor 96 even underleakage conditions such as high temperature andfurther includes a suitable filteringcapacitor and clamping diode toenhance and improve the operation of the circuit.

In addition, a disable line l05-is interconnected to the inputtransistor 102 ofthe monostable circuit. The disabled line 105 isconnected to the polarity detector 58 to permit actuation of themonostable circuit or module 57 only when circuit conditions are suchthat the related bridge network6 is to conduct; i.e., when there is apositive error voltage signal. The polarity detector 58in theillustrated embodiment of the invention may be any suitable circuitwhich normally applies a positive voltage to the transistor 102 ofsufficient magnitude to hold the circuit in the normal state regardlessof the output of the Nor" transistor 96. In order to permit an outputpulse, the signal at the disabled line 105 must drop to a logic "0"level. Thisin turn is connected directly by the polarity detector.

The input signal from the summing amplifier 22 is also connected to theintercept module 55 for the alternate bridge network 7. The interceptmodule 55 and related output modules for the bridge network 7 isessentially identical to that of the module 47 and correspondingtransistor and circuit element have been identified by correspondingprimed number.- The output of transistor is connected directly to a Nor"circuit transistor 96' which is also interconnected directly to theoutput of the common zero detector transistor 97. The output of the Nor"circuit transistor 96' is interconnected to control a similartransistorized monostable circuit of transistors 102' and 103' tocontrol the gate driver 29 for the alternate bridge network 7. Theoutput pulses 53 shown in FIG. 3 would thus be shifted 180 and beestablished when curves 43 and 48 are both at logic 1 levels. Thedisable line 105 connects transistor 102' to the negative polaritydetector 59 to enable network 7 only during the negative half cycle ofanode reference voltage. Thus, the intercept modules 47 and 55 incombination with the zero detector module 40 and the polarity detectors58 and 59 provide an alternate control of the two bridge networks 6 and7 to provide proper armature current to armature 4, depending upon thepolarity of the error signal in combination with the magnitude of thesummation of the error signal and the counter-electromotive forcesignal. This has been found to provide a very reliable and linearcontrol of the firing of the silicon controlled rectifiers and theoperation of the circuit.

The output of the several gating regulator boards are interconnected tocontrol the firing of the bridge networks which as shown in FIG. 5 areconstructed generally in accordance with applicants copendingapplication entitled GATING SYSTEM FOR CON- TROLLED RECTIFIER MEANS.Each network 6 and 7 includes six silicon controlled rectifiers 66-71connected as three phase full wave bridge in accordance with the knownconstruction. The gate to cathode circuit of each rectifier 66-71 isinterconnected to the gating regulator outputs.

The illustrated input transformer 15 is shown in FIG. 4 as a wye to wyecircuit connection. The wye to wye construction is preferred because ofthe lack of any signiticant phase shift in the secondary output andconsequently phasing of the control transformer unit for proper gatingis well defined. If a delta to wye configuration is employed, there isan inherent 30 phase shift in line to line voltages and consequentlycompensating circuitry must be provided. However, either system can beemployed.

The circuit 16 is a compensation and voltage transients suppressioncircuit associated with the full wave rectifier circuit. Generallycircuit 16 includes a connected circuitry including selenium thyrectordiodes 106 in parallel with a series connected resistance 107 andcapacitor 108 in each phase of the three phase transformer secondary.Further, inductors 17 connected one in each of the A.C. lines to therespective bridge inputs limits the di/dt effect during commutationintervals. These have been found particularly necessary in view of theuse of the thyrector diodes which have a substantial amount of inherentcapacitance. Inductance is not required in the D.C. circuit as thearmature inductance will always be sufficient to limit the di/dt effectduring the commutation or rectifier turn off period.

In the illustrated embodiment of the invention, the armature relatedsignal current is derived from three current transformers 109 each ofwhich includes a primary winding 110 connected in series in each of thephase lines and a secondary winding 111 providing a signal proportionalto the phase current. A protective resistor 112 may be connected inparallel with each secondary winding as illustrated. Each of the currenttransformers is similarlyconstructed and connected in the circuit andconsequently a single unit is described; it being readily understoodthat the other lines are similarly connected.

The secondary winding 111 is connected as the input to a full wavewheatstone bridge type diode rectifier 113, the output of which isconnected across a pair of series connected potentiometers 114 and 115.The three rectifiers 113 are connected in parallel to the three phasecurrents. The common junction of the series connected potentiometers 114and 115 are connected to a common reference 116 and each includes a tap117 and 118 respectively also interconnected to the common referenceline. The one or upper potentiometer 114 establishes the level of thepositive armature current signal while the lower potentiometer 115similarly establishes the level of the negative armature current signalwith respect to the common reference line 116. 1

The signals at lines 119 and 120 are the same regardless of thedirection of the armature current and consequently whether the positivearmature signal or the identifiednegative armature current signal isinserted in the circuit is separated and independently determined. Inthe illustrated embodiment of the present invention, the output of thepolarity detector units 58 and 59 are connected to control a pair ofgate units 121 and 122 which respectively connect the potentiometeroutput lines 119 and 120 to the summing amplifier 22. If a positivearmature current signal is desired, the gate 121 is enabled to transferthe signal while the negative gate unit-122 will be held in an offcondition. Any suitable gating system can be employed, the detailsthereof are not set forth. The polarity detector control is satisfactorybecause the negative armature current is always associated with theoperation of the bridge network 6 and the positive armature current isalways associated with the bridge network 7.

The voltage signal is derived directly across the armature 4 by a pairof series connected resistors 123 and 124 connected across the armature.The voltage signal appearing across the resistor l23 is fed, preferablythrough the isolating and filtering network 20, directly to the summingamplifier 22. The armature voltage inherently provides the necessarypolarity. The isolating and filtering networks for both armature andvoltage signals may be of a well-known variety such as a magneticamplifier unit with proper resistive capacitive filtering elements.

Although the details shown in the drawing of the input circuit and thelike full wave bridge rectifiers and the like are not essential, theillustrated circuit has been found to provide a highly satisfactory andcommercially practical motor control circuitestablishing accuratecontrol of armature current to within plus and minus 2 percent whiledelivering any current within the rating of the constant field voltagemotor regardless of line voltage or ambient temperature within givenspecifications.

Various modes of carrying out the invention are contemplated as beingwithin the scope of the following claims, particularly pointing out anddistinctly claiming the subject matter which is regarded as theinvention.

1 claim:

1. A motor control circuit for energizing of a motor having an armatureto maintain a regulated motor output, comprising command means toestablish a command voltage signal proportional to a desired motoroutput signal forming means having means coupled to the motor toestablish a first signal related to the actual motor output and thedesired output to define an error signal and current sensing means toestablish a second signal proportional to armature current,

control means for controlling the input power connection of said motorto an incoming power supply, and

actuating means for said control means connected to said signal formingmeans and having a first input means connected to receive said firstsignal and a second input connected to receive said second signal toproduce a net signal equal to the sum of the error signal and the signalproportional to the counterelectromotive force and connected to saidcontrol means and actuating said control means in accordance with thesummation of said first and second signals, said second signal being ofa polarity corresponding to the armature voltage for establishingessentially zero power input to said motor with said actual motor outputcorresponding to said desired output and providing a continuous positivetracking of the counterelectromotive force of the armature.

2. In a motor control circuit for controlling the energization of amotor having an armature with an armature current varying with the motorload in accordance with a feedback signal, comprising means to supplycurrent to the armature,

a first feedback signal means providing a signal proportional to theactual motor output,

a command signal unit,

a first comparing means having a pair of input means connected to thefirst feedback signal means and to the command signal unit andestablishing an error signal output proportional to the algebraicsummation thereof,

a second feedback signal means providing a corresponding current signalproportional to the motor armature current for all modes of motoroperation and the related resistance armature voltage drop of the motorand a voltage signal proportional to the motor armature voltage, and

a second comparing means having input means connected to said firstcomparing means and to the second feedback signal means and providing asummated error signal 'equal to the difference of the current signal andthe voltage signal algebraically added to the error signal with thecurrent signal polarity corresponding to the polarity of the firstfeedback signal means and connected to the means to supply current forcontrolling the current supply to the armature of said motor within therating of the motor.

3. In a motor control circuit for controlling the energization of amotor having an armature with an armature current varying with the motorload in accordance with a feedbacksignal, comprising a voltage sourcefor energizing of said armature,

a first voltage feedback signal means providing an armature voltagesignal proportional to the armature voltage,

a command signal unit establishing a voltage proportional to a desiredarmature voltage,

a first comparing means having a pair of input means connected to thefirst voltage feedback signal means and to the command signal unit andestablishing an error signal output proportional to the algebraicsummation thereof,

a second feedback signal means providing a corresponding current signalproportional to the motor armature current for all modes of motoroperation and the related resistance armature volt age drop of the motorand establish an IR drop voltage signal proportional to the motorarmature voltage drop, and

a second comparing means having input means connected to the first andsecond feedback signal means and with the [R drop voltage signalsubtracted from the armature voltage signal to provide a tracking signalproportional to the counterelectromotive force and connected to saidfirst comparing means to add the error signal to the tracking signal andprovide a summated error signal to the voltage source for continuouslycontrolling the current supply to the armature of said motor within therating of the motor.

4. The motor control circuit of claim 3 for controlling a reversiblemotor, having a pair of parallel connected gated rectifying networksconnected to energize said motor, said second comparing means connectedto said rectifying networks and said summated error signal controllinggating'of said networks, said first comparing means establishing adirect current 7. The motor control circuit of claim 3 having apolyphase alternating current input means, and a pair of gated networkseach including a plurality of gate controlled rectifiers connected inphase related pairs, said networks being connected in parallel andpolarized to conduct opposite load currents and connected between saidinput means and said motor, a gating regulator connected to said secondcomparing means and having a plurality of output means connected to saidpaired controlled rectifiers to control the firing thereof during eachcorresponding half cycle of the applied alternating current, said firstcomparing means establishing a direct current error signal outputrelated error signal output related to the relative polarities of theinput and proportional to the algebraic summation thereof, and

a selection means connected to first comparing means and said rectifyingnetworks to enable one network in response to a given polarity of theerror signal and the other network in response to an opposite polarityof the error signal. 5. The motor control circuit of claim 3 having analternating current input means and a pair of gated networks connectingsaid alternating current input means to said motor, and a gatingregulator connected to said second comparing means and to said gatednetworks and establishing a phased gating of said networks during eachhalf cycle of the alternating current in accordance with said summatederror signal.

6. The motor control circuit of claim 3 for controlling the powersupplied to the armature of a direct current motor, having analternating current input means and a pair of parallel rectifying gatednetworks connected in parallel to said input means and said motorarmature anda gating regulator connected to said second comparing meansand to both of said gated networks to simultaneously generate phase gatesignals during each half cycle of the alternating current, and

selection means responsive to said first named error signal andconnected to said regulator to operatively inhibit one of said gatesignals.

to the relative polarities of the input and proportional to thealgebraic summation thereof, and

a selection means connected to first comparing means and said rectifyingnetworks to enable one network in response to a given polarity of theerror signal and the other network in response to an opposite polarityof the error signal.

8. The motor control circuit of claim 3 having an alternating currentinput means and a pair of gated unidirectional conductive networksconnecting said input means to said motor, and a solid state logiccircuit having an alternating current input phase related to thealternating current input to said gated network and having means toestablish a series of time spaced pulses for gating said gated networkat a given time in each half cycle, and circuit means connected to saidlogic circuit and to said second means to vary said given time andestablish a zero current network output under all motor operationwherein said error signal is zero.

9. The motor control circuit of claim 3 having an alternating currentinput means, a pair of gated rectifier networks connecting said inputmeans to said motor, and a solid state logic circuit having analternating current input phase related to the alternating current inputto said gated rectifier networks and having a pair of pulse generatingchannels including a common input to said second comparing means andeach establishing a series of time spaced pulse trains for gating acorresponding network at a given time in each half cycle, and havingcorresponding pulses in said trains being spaced by with respect to saidinput means, and circuit means connected to said logic circuit and tosaid second means to vary said given time and establish a zero networkcurrent under all motor operation wherein said error signal is zero.

10. The motor control circuit of claim 3 having an alternating currentinput means and a pair of gated networks connecting said input means tosaid motor, and a solid state logic circuit having an alternatingcurrent input phase related to the alternating current input to saidgated networks and having means to establish a series of time spacedpulses for gating said networks in at a given time'in each half cycle,and circuit means connected to said logic circuit and to said secondmeans to vary said given time and establish a zero current under allmotor operation wherein said error signal is zero.

1 l. The motor control circuit of claim 3 having an alternating currentinput means and a gated rectifying network connecting said input meansto said motor, and a gating regulator having a binary logic outputwhereby a pulse is generated by successive timed changes in the outputbetween two magnitudes, said gating regulator having a referencealternating current input having zero crossover points phase shifted 30to lead the alternating current input to the gated network andconstructed to generate a first edge of a pulse at each zero crossoverpoint, a reference alternating current phase shifted to lag saidalternating current input to said network by 60 and connected in saidgating regulator to form the second edge of said pulse and to limit thefiring during each half cycle to a given maximum output point, and adirect current bias signal source adapted to be connected to said gatingregulator to establish an effective zero crossover point in phase withthe zero crossover point of the alternating current input to the gatednetwork in the absence of a summated error signal, and circuit means toconnect the bias signal source and said second means to said gatingregulator to establish a signal intercept with said referencealternating current input and thereby establish said first edge of thepulse in accordance with said bias signal and said summated signal.

12. The motor control circuit of claim 3 having a polyphase alternatingcurrent input means, a pair of similar gated rectifier networksconnected in parallel to said input means and to said motor, and eachhaving a pair of gated devices for each phase of said input means, and agating regulator having a binary logic output channel for controlling apair of gated devices for one phase of each network, each channel ofsaid gating regulator having a zero detector and a first interceptdetector for one network and a second intercept detector for the secondnetwork, a first reference alternating current input connected to saidintercept detector and having zero crossover points phase shifted 30 tolead the alternating current input to the related pair of gated devicesof said networks and constructed to generate a change in the logic levelof the intercept detectors at each zero crossover point, a secondreference alternating current phase shifted to lag said alternatingcurrent input to said network by 60 and connected to said zero detectorto change the logic level to the zero detector at each zero crossoverpoint, to limit the firing during each half cycle to a given maximumoutput point, and a direct current bias source connected to saidintercept detectors to establish an effective zero crossover point inphase with the zero crossover point of the alternating current input tothe gated network in the absence of a summated error, and circuit meansto connect said second comparing means to said intercept detectors toestablish a signal intercept with said reference altemating currentinput and thereby establish said change in logic level in,accordancewith said bias signal and said summated signal, first pulse means tocontrol the first network and connected to said first intercept detectorand said zero detector to establish a pulse signal during the positivehalf cycle of the second reference signal, second pulse means to controlthe second network and connected to said second intercept detector andsaid zero detector to establish a pulse signal during the negative halfcycle of the second reference signal.

13. The motor control circuit of claim 12, having a gate'meansconnecting said first pulse means to said first network and a secondgate connecting said second pulse means to said second network, saidfirst comparing means establishing a direct current output having apolarity related to the relative polarities and magnitudes of the inputsthereto, a polarity detection means connected to the output of the firstcomparing means and to said gate means to selectively enable one of saidgate means in response to a first polarity and the other in response tothe second polarity.

14. The motor control circuit of claim 12, wherein said interceptdetectors include a load detector amplifier having an input means, saidfirst reference altemating current being applied to said input means andbiasing said amplifier to a first signal logic level during the positivehalf cycle and a second signal logic level during the negative halfcycle, said direct current bias source being connected to said inputmeans and biasing said amplifier to -increase the-period of one of saidsignal levels and decrease the period of the other of said signallevels, and said second comparing means being connected to said inputmeans to vary the direct current bias to said input and thereby vary theintercept with said first reference alternating current to control thephase at which said signal logic level changes.

15. In a motor control circuit for a motor having an armature connectedin an armature circuit to an alternating current supply, command meansto establish a command voltage signal proportional to a desired motoroperation, first voltage feedback means to establish a feedback signalproportional to the armature voltage, first summating means connected tosaid command means and to said feedback means to provide an errorvoltage signal, second feedback means having a first current sensingunit coupled to the armature circuit to establish a correspondingfeedback signal for all modes of motor operation proportional to thearmature current voltage drop of the motor armature and a voltage signalproportional to the armature voltage, a second summating means connectedto said first summating means and to said second feedback means toprovide a summated control signal proportional to the algebraic sum ofsaid signal and including the difference of said armature voltage andsaid armature current voltage drop added to said error signal toestablish continuous tracking of the counterelectromotive voltage ofsuch armature, gated means connected in said armature circuit and havingan alternating current input and a periodic output, and means connectingthe gated means to said second summating means and having an altematingcurrent reference voltage signal and gating said gating means to conductin accordance with the control signal intercept with said voltage signalto control the motor for all modes of motor operation.

16. The motor control circuit of claim 15, wherein said gated meansincludes a pair of full wave bridge networks employing a siliconcontrolled rectifier in each leg of the network, said networks beingconnected parallel to the motor-and to supply voltage means and a firstgated means being connected to conduct a forward torque armature currentand the second gated means being connected to conduct a reverse torquearmature current, said last named means including an intercept detectorfor a pair of related rectifiers in each network and a common zerocurrent detector for each pair of intercept detectors, each of saidintercept detectors being connected to an alternating current referencevoltage in selected phase relationship to the anode reference voltagefrom said supply voltage means and to a direct current bias meansselected in accordance with said selected phase relationship, the outputmeans of said summing amplifier establishing a direct current signal andbeing connected in common to said intercept detector, said common zerocurrent-detector ineluding an amplifying device and being connected toan alternating current reference voltage in selected phase relationshipto said anode reference supply voltage, logic circuit means for each ofsaid controlled rectifiers and having a first input means connected to acorresponding intercept detector and a second input means connected to acorresponding zero current detector and producing an output signal inresponse to preselected related inputs, pulse forming means connectedone each to each of said logic circuit means and to the correspondingpair of rectifiers to establish simultaneous firing of the pair ofrectifiers, said error amplifier providing a given polarity error signalfor forward torque and a reverse polarity error signal for reversetorque, and polarity sensing means connected to the error amplifier andto said pulse forming means to selectively bias the networks such thatonly one network is enabled in response to one polarity of error signaland the second network is enabled in response to the opposite polarityof error signal.

1. A motor control circuit for energizing of a motor having an armatureto maintain a regulated motor output, comprising command means toestablish a command voltage signal proportional to a desired motoroutput signal forming means having means coupled to the motor toestablish a first signal related to the actual motor output and thedesired output to define an error signal and current sensing means toestablish a second signal proportional to armature current, controlmeans for controlling the input power connection of said motor to anincoming power supply, and actuating means for said control meansconnected to said signal forming means and having a first input meansconnected to receive said first signal and a second input connected toreceive said second signal to produce a net signal equal to the sum ofthe error signal and the signal proportional to the counterelectromotiveforce and connected to said control means and actuating said controlmeans in accordance with the summation of said first and second signals,said second signal being of a polarity corresponding to the armaturevoltage for establishing essentially zero power input to said motor withsaid actual motor output corresponding to said desired output andproviding a continuous positive tracking of the counterelectromotiveforce of the armature.
 1. A motor control circuit for energizing of amotor having an armature to maintain a regulated motor output,comprising command means to establish a command voltage signalproportional to a desired motor output signal forming means having meanscoupled to the motor to establish a first signal related to the actualmotor output and the desired output to define an error signal andcurrent sensing means to establish a second signal proportional toarmature current, control means for controlling the input powerconnection of said motor to an incoming power supply, and actuatingmeans for said control means connected to said signal forming means andhaving a first input means connected to receive said first signal and asecond input connected to receive said second signal to produce a netsignal equal to the sum of the error signal and the signal proportionalto the counterelectromotive force and connected to said control meansand actuating said control means in accordance with the summation ofsaid first and second signals, said second signal being of a polaritycorresponding to the armature voltage for establishing essentially zeropower input to said motor with said actual motor output corresponding tosaid desired output and providing a continuous positive tracking of thecounterelectromotive force of the armature.
 2. In a motor controlcircuit for controlling the energization of a motor having an armaturewith an armature current varying with the motor load in accordance witha feedback signal, comprising means to supply current to the armature, afirst feedback signal means providing a signal proportional to theactual motor output, a command signal unit, a first comparing meanshaving a pair of input means connected to the first feedback signalmeans and to the command signal unit and establishing an error signaloutput proportional to the algebraic summation thereof, a secondfeedback signal means providing a corresponding current signalproportional to the motor armature current for all modes of motoroperation and the related resistance armature voltage drop of the motorand a voltage signal proportional to the motor armature voltage, and asecond comparing means having input means connected to said firstcomparing means and to the second feedback signal means and providing asummated error signal equal to the difference of the current signal andthe voltage signal algebraically added to the error signal with thecurrent signal polarity corresponding to the polarity of the firstfeedback signal means and connected to the means to supply current forcontrolling the current supply to the armature of said motor within therating of the motor.
 3. In a motor control circuit for controlling theenergization of a motor having an armature with an armature currentvarying with the motor load in accordance with a feedback signal,comprising a voltage source for energizing of said armature, a firstvoltage feedback signal means providing an armature voltage signalproportional to the armature voltage, a command signal unit establishinga voltage proportional to a desired armature voltage, a first comparingmeans having a pair of input means connected to the first voltagefeedback signal means and to the command signal unit and establishing anerror signal output proportional to the algebraic summation thereof, asecond feedback signal means providing a corresponding current signalproportional to the motor armature current for all modes of motoroperation and the related resistance armature voltage drop of the motorand establish an IR drop voltage signal proportional to the motorarmature voltage drop, and a second comparing means having input meansconnected to the first and second feedback signal means and with the IRdrop voltage signal subtracted from the armature voltage signal toprovide a tracking signal proportional to the counterelectromotive forceand connected to said first comparing means to add the error signal tothe tracking signal and provide a summated error signal to the voltagesource for continuously controlling the current supply to the armatureof said motor within the rating of the motor.
 4. The motor controlcircuit of claim 3 for controlling a reversible motor, having a pair ofparallel connected gated rectifying networks connected to energize saidmotor, said second comparing means connected to said rectifying networksand said summated error signal controlling gating of said networks, saidfirst comparing means establishing a direct current error signal outputrelated to the relative polarities of the input and proportional to thealgebraic summation thereof, and a selection means connected to firstcomparing means and said rectifying networks to enable one network inresponse to a given polarity of the error signal and the other networkin response to an opposite polarity of the error signal.
 5. The motorcontrol circuit of claim 3 having an alternating current input means anda pair of gated networks connecting said alternating current input meansto said motor, and a gating regulator connected to said second comparingmeans and to said gated networks and establishing a phased gating ofsaid networks during each half cycle of the alternating current inaccordance with said summated error signal.
 6. The motor control circuitof claim 3 for controlling the power supplied to the armature of adirect current motor, having an alternating current input means and apair of parallel rectifying gated networks connected in parallel to saidinput means and said motor armature and a gating regulator connected tosaid second comparing means and to both of said gated networks tosimultaneously generate phase gate signals during each half cycle of thealternating current, and selection means responsive to said first namederror signal and connected to said regulator to operatively inhibit oneof said gate signals.
 7. The motor control circuit of claim 3 having apolyphase alternating current input means, and a pair of gated networkseach including a plurality of gate controlled rectifiers connected inphase related pairs, said networks being conneCted in parallel andpolarized to conduct opposite load currents and connected between saidinput means and said motor, a gating regulator connected to said secondcomparing means and having a plurality of output means connected to saidpaired controlled rectifiers to control the firing thereof during eachcorresponding half cycle of the applied alternating current, said firstcomparing means establishing a direct current error signal outputrelated to the relative polarities of the input and proportional to thealgebraic summation thereof, and a selection means connected to firstcomparing means and said rectifying networks to enable one network inresponse to a given polarity of the error signal and the other networkin response to an opposite polarity of the error signal.
 8. The motorcontrol circuit of claim 3 having an alternating current input means anda pair of gated unidirectional conductive networks connecting said inputmeans to said motor, and a solid state logic circuit having analternating current input phase related to the alternating current inputto said gated network and having means to establish a series of timespaced pulses for gating said gated network at a given time in each halfcycle, and circuit means connected to said logic circuit and to saidsecond means to vary said given time and establish a zero currentnetwork output under all motor operation wherein said error signal iszero.
 9. The motor control circuit of claim 3 having an alternatingcurrent input means, a pair of gated rectifier networks connecting saidinput means to said motor, and a solid state logic circuit having analternating current input phase related to the alternating current inputto said gated rectifier networks and having a pair of pulse generatingchannels including a common input to said second comparing means andeach establishing a series of time spaced pulse trains for gating acorresponding network at a given time in each half cycle, and havingcorresponding pulses in said trains being spaced by 180* with respect tosaid input means, and circuit means connected to said logic circuit andto said second means to vary said given time and establish a zeronetwork current under all motor operation wherein said error signal iszero.
 10. The motor control circuit of claim 3 having an alternatingcurrent input means and a pair of gated networks connecting said inputmeans to said motor, and a solid state logic circuit having analternating current input phase related to the alternating current inputto said gated networks and having means to establish a series of timespaced pulses for gating said networks in at a given time in each halfcycle, and circuit means connected to said logic circuit and to saidsecond means to vary said given time and establish a zero current underall motor operation wherein said error signal is zero.
 11. The motorcontrol circuit of claim 3 having an alternating current input means anda gated rectifying network connecting said input means to said motor,and a gating regulator having a binary logic output whereby a pulse isgenerated by successive timed changes in the output between twomagnitudes, said gating regulator having a reference alternating currentinput having zero crossover points phase shifted 30* to lead thealternating current input to the gated network and constructed togenerate a first edge of a pulse at each zero crossover point, areference alternating current phase shifted to lag said alternatingcurrent input to said network by 60* and connected in said gatingregulator to form the second edge of said pulse and to limit the firingduring each half cycle to a given maximum output point, and a directcurrent bias signal source adapted to be connected to said gatingregulator to establish an effective zero crossover point in phase withthe zero crossover point of the alternating current input to the gatednetwork in the absence of a summated error signal, and circuit means toconnect The bias signal source and said second means to said gatingregulator to establish a signal intercept with said referencealternating current input and thereby establish said first edge of thepulse in accordance with said bias signal and said summated signal. 12.The motor control circuit of claim 3 having a polyphase alternatingcurrent input means, a pair of similar gated rectifier networksconnected in parallel to said input means and to said motor, and eachhaving a pair of gated devices for each phase of said input means, and agating regulator having a binary logic output channel for controlling apair of gated devices for one phase of each network, each channel ofsaid gating regulator having a zero detector and a first interceptdetector for one network and a second intercept detector for the secondnetwork, a first reference alternating current input connected to saidintercept detector and having zero crossover points phase shifted 30* tolead the alternating current input to the related pair of gated devicesof said networks and constructed to generate a change in the logic levelof the intercept detectors at each zero crossover point, a secondreference alternating current phase shifted to lag said alternatingcurrent input to said network by 60* and connected to said zero detectorto change the logic level to the zero detector at each zero crossoverpoint, to limit the firing during each half cycle to a given maximumoutput point, and a direct current bias source connected to saidintercept detectors to establish an effective zero crossover point inphase with the zero crossover point of the alternating current input tothe gated network in the absence of a summated error, and circuit meansto connect said second comparing means to said intercept detectors toestablish a signal intercept with said reference alternating currentinput and thereby establish said change in logic level in accordancewith said bias signal and said summated signal, first pulse means tocontrol the first network and connected to said first intercept detectorand said zero detector to establish a pulse signal during the positivehalf cycle of the second reference signal, second pulse means to controlthe second network and connected to said second intercept detector andsaid zero detector to establish a pulse signal during the negative halfcycle of the second reference signal.
 13. The motor control circuit ofclaim 12, having a gate means connecting said first pulse means to saidfirst network and a second gate connecting said second pulse means tosaid second network, said first comparing means establishing a directcurrent output having a polarity related to the relative polarities andmagnitudes of the inputs thereto, a polarity detection means connectedto the output of the first comparing means and to said gate means toselectively enable one of said gate means in response to a firstpolarity and the other in response to the second polarity.
 14. The motorcontrol circuit of claim 12, wherein said intercept detectors include aload detector amplifier having an input means, said first referencealternating current being applied to said input means and biasing saidamplifier to a first signal logic level during the positive half cycleand a second signal logic level during the negative half cycle, saiddirect current bias source being connected to said input means andbiasing said amplifier to increase the period of one of said signallevels and decrease the period of the other of said signal levels, andsaid second comparing means being connected to said input means to varythe direct current bias to said input and thereby vary the interceptwith said first reference alternating current to control the phase atwhich said signal logic level changes.
 15. In a motor control circuitfor a motor having an armature connected in an armature circuit to analternating current supply, command means to establish a command voltagesignal proportional to a desirEd motor operation, first voltage feedbackmeans to establish a feedback signal proportional to the armaturevoltage, first summating means connected to said command means and tosaid feedback means to provide an error voltage signal, second feedbackmeans having a first current sensing unit coupled to the armaturecircuit to establish a corresponding feedback signal for all modes ofmotor operation proportional to the armature current voltage drop of themotor armature and a voltage signal proportional to the armaturevoltage, a second summating means connected to said first summatingmeans and to said second feedback means to provide a summated controlsignal proportional to the algebraic sum of said signal and includingthe difference of said armature voltage and said armature currentvoltage drop added to said error signal to establish continuous trackingof the counterelectromotive voltage of such armature, gated meansconnected in said armature circuit and having an alternating currentinput and a periodic output, and means connecting the gated means tosaid second summating means and having an alternating current referencevoltage signal and gating said gating means to conduct in accordancewith the control signal intercept with said voltage signal to controlthe motor for all modes of motor operation.